The present invention relates to a semiconductor device and more particularly to the structure of a peripheral circuit section of a nonvolatile semiconductor memory.
A flash memory generally includes various types of delay circuits necessary for operations, a write/erase high-voltage stabilization circuit, and a reference voltage generation circuit as well as memory cells in a chip. The flash memory therefore requires resistance elements constituting these circuits. These resistance elements generally have ohmic characteristics. The resistance elements are formed in almost the same step as that of forming a memory cell in a chip in order to improve the efficiency of a manufacturing process.
Referring to FIGS. 7A and 7B, an operation of the write/erase high-voltage stabilization circuit will be described as one example of a circuit using the above resistance elements. FIG. 7A schematically shows the write/erase high-voltage stabilization circuit, and FIG. 7B shows respective voltages generated when the circuit performs its operations. As shown in FIG. 7A, the write/erase high-voltage stabilization circuit is a feedback circuit for controlling an output voltage of a booster circuit. More specifically, resistance elements R1 and R2 are connected to an output terminal of the booster circuit including a charge pump circuit. The resistance elements R1 and R2 divide the output voltage of the booster circuit to generate a voltage Va. The voltage Va is compared with a reference voltage Vref in an operational amplifier OP1 to generate a control signal "PHgr" 1. In response to the control signal "PHgr" 1, the booster circuit is operated to control its output voltage.
If the voltage Va becomes lower than the reference voltage Vref as shown in FIG. 7B, the booster circuit in FIG. 7A operates. If the voltage Va becomes higher than the reference voltage Vref, the booster circuit stops its boost operation and a feedback operation is performed to increase the potential. The output voltage is thus held at a required voltage Vpp.
If, however, the capacitance between the resistance elements R1 and R2 and the nodes of the other elements in a semiconductor substrate is large, a delay due to the CR time constant increases. Then, the feedback operation is delayed and the output voltage greatly deviates from the required voltage Vpp. This hinders the flash memory from performing stable and high-speed operation. The smaller the capacity between the resistance elements and the nodes of the other elements, the higher the precision of the voltage stabilization circuit.
FIG. 8 is a schematic cross-sectional view of a prior art flash memory. In this flash memory, an element isolation region 22 is formed in a silicon substrate 21 and a gate oxide film 24 is formed in an element region 23 of the cell section. After that, a first gate electrode 25 is deposited. The first gate electrode 25 is used as a floating gate in the cell section and a resistance element 25a in the peripheral circuit section. In FIG. 8, reference numeral 26 indicates a first insulation film, 27 shows a second gate electrode, 28 denotes an interlayer insulation film, and 30 represents a wiring layer.
In the cell section, the first gate electrode can be formed of two layers. In the peripheral circuit section, the resistance element 25a can be formed of gate materials of the upper one of the two layers.
Since the resistance element 25a is formed on the thick element isolation region 22, the capacitance between the resistance element 25a and the nodes of the other elements in the semiconductor substrate can be decreased.
In the flash memory so constituted, the first gate electrode 25 is formed after forming the element isolation region 22. As shown in FIG. 8, therefore, the first gate electrode 25 extends to the element isolation region 22. Consequently, the element isolation region 22 of the cell section cannot be decreased in size and the elements are difficult to miniaturize further.
The present invention has been developed to resolve the above problem and an object thereof is to provide a semiconductor memory device capable of reducing the capacitance between a resistance element and a substrate in a peripheral circuit section even when a first gate electrode is isolated in self-alignment.
The object of the invention is attained by the following constituting elements:
A semiconductor memory device according to a first aspect of the present invention comprises a semiconductor substrate, an element isolation region provided in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element provided on the element isolation region, the resistance element and the second gate electrode being formed of a same conductive film.
A semiconductor memory device according to a second aspect of the present invention comprises a semiconductor substrate, an element isolation region provided in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, and a resistance element provided on the element isolation region and formed of a conductive film, wherein the semiconductor substrate has impurity concentration profile which is set to be constant or be lower in accordance with the depth of the semiconductor substrate getting shallower toward the region corresponding to the resistance element.
A semiconductor memory device according to a third aspect of the present invention comprises a semiconductor substrate of a first conductivity type, an element isolation region provided in the semiconductor substrate, for isolating an element region, a resistance element provided on the element isolation region and formed of a conductive film, and an opposite-conductivity-type diffusion layer of a second conductivity type that is opposite to the first conductivity type of the semiconductor substrate, the opposite-conductivity-type diffusion layer being formed in the element region adjacent to the element isolation region on which the resistance element is provided.
A method of manufacturing a semiconductor memory device according to a fourth aspect of the present invention comprises the steps of forming a gate oxide film and a first conductive film on a memory cell array region and a peripheral circuit region of a semiconductor substrate, forming a mask material on the first conductive film where the cell transistor is to be formed in the memory cell array region, forming trenches by etching the first conductive film and the gate oxide film with the mask material, forming an insulation film in the trenches in the memory cell array region and the peripheral circuit region, removing the mask material, forming a first insulation film on at least the first conductive film, forming a second conductive film on the first insulation film in the memory cell array region and the peripheral circuit region, and forming the resistance element by etching the second conductive film on the peripheral region.
In the semiconductor memory device of the present invention described above, the capacitance between the resistance element and the substrate in the peripheral circuit section can be reduced even when the first gate electrode is isolated in self-alignment.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.